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<TITLE>Cracking DES: Chapter 8 - Hardware Board Schematics</TITLE>
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<BLOCKQUOTE>
<H1>
<A NAME="8">8</A>
</H1>
<H2>
<I>Hardware Board Schematics</I>
</H2>
<P>
<I>In This chapter:</I>
<P>
<UL>
<LI>
<I>Board Schematics</I>
</UL>
<UL>
<LI>
<I>Sun-4/470 backplane modifications</I>
</UL>
<UL>
<LI>
<I>PC Interfaces</I>
</UL>
<UL>
<LI>
<I>Errata</I>
</UL>
<P>
<P>
This chapter contains schematic diagrams of the printed-circuit boards that
we designed and built for the DES Cracker. It also includes a few other details
about the hardware.
<P>
Each hardware board holds 64 DES Cracker chips. In this schematic, we only
show how 8 of the chips are wired. The rest are wired almost identically.
Each "All Active Out" pin is daisy-chained to the next "All Active In" pin.
The "Chip ID" pins on each chip are connected directly to either ground or
power, to tell the chip its binary chip number among all the chips on the
board. If you examine these pins for the eight chips shown, you'll see how
they change.
<P>
The boards fit into card-cages which are connected to each other and to the
host computer by a 50-pin ribbon cable. The card-cages are modified Sun-4/470
server card cages. The modifications we made to their backplanes are detailed
toward the end of the chapter.
<H3>
<I>Board Schematics</I>
</H3>
<P>
The schematics begin on the next page. <I>[Note: schematics enlarged 150%
to improve readbility.]</I>
<P>
<I>8-1</I>
<P>
<HR>
<P>
<I>8-2</I>
<P>
<IMG WIDTH="910" SRC="des8-1.jpg" HEIGHT="716">
<P>
<HR>
<P>
<I>8-3</I>
<P>
<IMG WIDTH="915" SRC="des8-2.jpg" HEIGHT="715">
<P>
<HR>
<P>
<I>8-4</I>
<P>
<IMG WIDTH="910" SRC="des8-3.jpg" HEIGHT="716">
<P>
<HR>
<P>
<I>8-5</I>
<P>
<IMG WIDTH="910" SRC="des8-4.jpg" HEIGHT="715">
<P>
<HR>
<P>
<I>8-6</I>
<P>
<IMG WIDTH="912" SRC="des8-5.jpg" HEIGHT="717">
<P>
<HR>
<P>
<I>8-7</I>
<P>
<IMG WIDTH="911" SRC="des8-6.jpg" HEIGHT="717">
<P>
<HR>
<P>
<I>8-8</I>
<P>
<IMG WIDTH="909" SRC="des8-7.jpg" HEIGHT="715">
<P>
<HR>
<P>
<I>8-9</I>
<P>
<IMG WIDTH="913" SRC="des8-8.jpg" HEIGHT="718">
<P>
<HR>
<P>
<I>8-10</I>
<H3>
<I>Sun-4/470 backplane modifications</I>
</H3>
<P>
The first DES Cracker uses several chassis recycled from Sun-4/470 servers
to hold its boards. Each chassis contains a card cage, power supplies, fans,
and covers. In the card cage there is a backplane, which is a printed circuit
board that holds the connectors for each board that can be plugged into the
card cage. Each row has connectors for 12 slots numbered from 1 to 12. The
card cage is sized for "9U" VMEbus boards, each of which has three large
96-pin connectors. Therefore, the backplane also has three 96-pin connectors
per board, called P1, P2, and P3. Each of these 96-pin connectors has three
rows of 32 pins inside it, called Rows A, B, and C.
<P>
We modified the backplane as follows:
<P>
Top Row (P1): No modification. We just use this signal from our boards to
these connectors.
<P>
Middle Row (P2): No modification. We just use this as a board holder. There
is no signal from our boards to these connectors.
<P>
Bottom Row (P3): Power and signaling for the DES Cracker boards, as follows:
<P>
<TABLE BORDER CELLPADDING="12">
<TR>
<TD COLSPAN="3"><P ALIGN="Center">
Table 8-1: Signal assignments on bottom connectors</TD>
</TR>
<TR>
<TD>Row A</TD>
<TD>Original Assignment</TD>
<TD>New Assignment</TD>
</TR>
<TR>
<TD>Pin 1 to 25</TD>
<TD>+5 Volts</TD>
<TD>Supply voltage for DES Cracker chips</TD>
</TR>
<TR>
<TD>Pin 26 to 27</TD>
<TD>+12 Volts</TD>
<TD>Not used</TD>
</TR>
<TR>
<TD>Pins 28 to 29</TD>
<TD>-12 Volts</TD>
<TD>Not used</TD>
</TR>
<TR>
<TD>Pins 30 to 32</TD>
<TD>-5 Volts</TD>
<TD>Not used</TD>
</TR>
<TR>
<TD><P ALIGN="Center">
Row B</TD>
<TD>Original Assignment</TD>
<TD>New Assignment</TD>
</TR>
<TR>
<TD>Pin 1</TD>
<TD>Reserved</TD>
<TD>Not used</TD>
</TR>
<TR>
<TD>Pin 2</TD>
<TD>Reserved</TD>
<TD>Not used</TD>
</TR>
<TR>
<TD>Pin 3</TD>
<TD>Reserved</TD>
<TD>Reset (C_RST)</TD>
</TR>
<TR>
<TD>Pin 4</TD>
<TD>Reserved</TD>
<TD>Read Strobe (C_RDB)</TD>
</TR>
<TR>
<TD>Pin 5</TD>
<TD>Reserved</TD>
<TD>Write Strobe (C_WRB)</TD>
</TR>
<TR>
<TD>Pin 6</TD>
<TD>Reserved</TD>
<TD>Address Latch Enable (C_AEN)</TD>
</TR>
<TR>
<TD>Pin 7</TD>
<TD>Reserved</TD>
<TD>Control_1 (C_CNT1) or C_ADRSELB</TD>
</TR>
<TR>
<TD>Pin 8</TD>
<TD>Reserved</TD>
<TD>Control_2 (C_CNT2) or C_CSB</TD>
</TR>
<TR>
<TD>Pin 9</TD>
<TD>Reserved</TD>
<TD>Data 7 (C_D7)</TD>
</TR>
<TR>
<TD>Pin 10</TD>
<TD>Reserved</TD>
<TD>Data 6 (C_D6)</TD>
</TR>
<TR>
<TD>Pin 11</TD>
<TD>Reserved</TD>
<TD>Data 5 (C_D5)</TD>
</TR>
<TR>
<TD>Pin 12</TD>
<TD>Reserved</TD>
<TD>Data 4 (C_D4)</TD>
</TR>
<TR>
<TD>Pin 13</TD>
<TD>Reserved</TD>
<TD>Data 3 (C_D3)</TD>
</TR>
<TR>
<TD>Pin 14</TD>
<TD>Reserved</TD>
<TD>Data 2 (C_D2)</TD>
</TR>
<TR>
<TD>Pin 15</TD>
<TD>Reserved</TD>
<TD>Data 1 (C_D1)</TD>
</TR>
</TABLE>
<P>
<HR>
<P>
<I>8-1</I>
<P>
<TABLE BORDER CELLPADDING="12">
<TR>
<TD COLSPAN="3"><P ALIGN="Center">
Table 8-1: Signal assignments on bottom connectors (continued)</TD>
</TR>
<TR>
<TD>Pin 16</TD>
<TD>Reserved</TD>
<TD>Data 0 (C_D0)</TD>
</TR>
<TR>
<TD>Pin 17</TD>
<TD>Reserved</TD>
<TD>Address 7 (C_A7)</TD>
</TR>
<TR>
<TD>Pin 18</TD>
<TD>Reserved</TD>
<TD>Address 6 (C_A6)</TD>
</TR>
<TR>
<TD>Pin 19</TD>
<TD>Reserved</TD>
<TD>Address 5 (C_A5)</TD>
</TR>
<TR>
<TD>Pin 20</TD>
<TD>Reserved</TD>
<TD>Address 4 (C_A4)</TD>
</TR>
<TR>
<TD>Pin 21</TD>
<TD>Reserved</TD>
<TD>Address 3 (C_A3)</TD>
</TR>
<TR>
<TD>Pin 22</TD>
<TD>Reserved</TD>
<TD>Address 2 (C_A2)</TD>
</TR>
<TR>
<TD>Pin 23</TD>
<TD>Reserved</TD>
<TD>Reserved Address 1 (C_A1)</TD>
</TR>
<TR>
<TD>Pin 24</TD>
<TD>Reserved</TD>
<TD>Address 0 (C_A0)</TD>
</TR>
<TR>
<TD>Pin 25</TD>
<TD>Reserved</TD>
<TD>GND</TD>
</TR>
<TR>
<TD>Pin 26</TD>
<TD>Reserved</TD>
<TD>GND</TD>
</TR>
<TR>
<TD>Pin 27</TD>
<TD>Reserved</TD>
<TD>GND</TD>
</TR>
<TR>
<TD>Pin 28</TD>
<TD>Reserved</TD>
<TD>GND</TD>
</TR>
<TR>
<TD>Pin 29</TD>
<TD>Reserved</TD>
<TD>GND</TD>
</TR>
<TR>
<TD>Pin 30</TD>
<TD>Reserved</TD>
<TD>GND</TD>
</TR>
<TR>
<TD>Pin 31</TD>
<TD>Reserved</TD>
<TD>+5 V supply to all Interface ICs</TD>
</TR>
<TR>
<TD>Pin 32</TD>
<TD>Reserved</TD>
<TD>+5 V supply to all Interface ICs</TD>
</TR>
<TR>
<TD><P ALIGN="Center">
Row C</TD>
<TD>Original Assignment</TD>
<TD>New Assignment</TD>
</TR>
<TR>
<TD>Pins 1 to 25</TD>
<TD>GND</TD>
<TD>GND</TD>
</TR>
<TR>
<TD>Pins 26 to 27</TD>
<TD>+12 Volts</TD>
<TD>Not used</TD>
</TR>
<TR>
<TD>Pins 28 to 29</TD>
<TD>-12 Volts</TD>
<TD>Not used</TD>
</TR>
<TR>
<TD>Pins 30 to 32</TD>
<TD>-5 Volts</TD>
<TD>Not used</TD>
</TR>
</TABLE>
<P>
<P>
Row A, pins 1-25 provide the supply voltage for the DES Cracker chips. The
supply is normally +5 Volts.
<P>
The chips can be run on a lower voltage, to reduce power consumption and
heat generation. In that case, two voltages must be supplied. The lower voltage
for the DES Cracker chips is supplied on Row A, pins 1-25. +5 volts is supplied
to the interface circuitry on Row B, pins 31 and 32. In low voltage operation,
Jumper JP1 on each of the DES boards must be removed. If the DES chips are
using +5 Volts, then no external power connects to Row B, pins 31 and 32,
and Jumper JP1 on each of the DES boards is connected.
<H3>
<I>Physical Modifications on P3 Bus (Bottom Row)</I>
</H3>
<P>
The P3 bus (bottom row) of the backplane has 12 slots. Some of these slots
are wired to their neighboring slots, forming a bus. In its original Sun
configuration, the P3 bus was mainly used for a high-speed memory bus between
the CPU board and the memory boards. It was divided into 4 independent groups:
<P>
Group 1
<BLOCKQUOTE>
This group has 7 slots (from 1 to 7) which have their Row B's bussed together.
</BLOCKQUOTE>
<P>
<HR>
<P>
<I>8-12</I>
<P>
Group 2
<BLOCKQUOTE>
This has only slot 8. Its Row B did not connect to any other.
</BLOCKQUOTE>
<P>
Group 3
<BLOCKQUOTE>
This has only slot 9. Its Row B did not connect to any other.
</BLOCKQUOTE>
<P>
Group 4
<BLOCKQUOTE>
This group has 3 slots (from 10 to 12) which have their Row B's bussed together.
</BLOCKQUOTE>
<P>
We modified the backplane to connect each of these four groups together,
so that P3 Row B connects from slot to slot along the whole backplane.
<P>
On both slot 1 and slot 12 we added a dual-row header to the P3 connector,
Rows B and C (signals and grounds), so that a 50-pin ribbon cable can connect
to the bus. These headers allow each chassis to be cabled to the next chassis,
and also allow the first chassis to be cabled to a general purpose computer,
where the software that controls the DES Cracker runs.
<P>
On slot 11, we also added a dual-row header to the P3 connector, Rows A and
B (Supply voltage and signals), to let us install termination resistors when
no ribbon cable is attached to Slot 12. These protect the integrity of the
signals on the bus.
<H3>
<I>PC Interfaces</I>
</H3>
<P>
The first chassis connects to the controlling computer via a ribbon cable,
which attaches to the dual-row header installed on Slot 1. This cable leads
to a plug-in hardware card which provides three parallel I/O ports. The software
talks to this card, causing it to write commands to the ribbon cable, or
read results back from the ribbon cable. The software runs in an ordinary
IBM PC, and could be ported to other general purpose computers.
<P>
Our project used either of two interface cards. Both are from National
Instruments Corporation of Austin, Texas, reachable at
<A HREF="http://www.natinst.com/">http://www.natinst.com</A> or +1 512 794
0100. Their PC-AT bus interface card is called the PC-DIO-24, order number
777368-01. For laptops, a "PC card" (PCMCIA) interface is also available,
the DAQCard-DIO-24, order number 776912-01. This card requires the PSH27-SOF-D1
cable, with order number 776989-01.
<P>
Other parallel interface cards that provide 24 bit I/O could also be made
to work.
<P>
<HR>
<P>
<I>8-13</I>
<H3>
<I>Errata</I>
</H3>
<P>
This page contains notes about errors detected late in the hardware or software
published herein.
<P>
<B><I>Chip select for reading</I></B>
<P>
The DES Cracker chips do not properly tristate their data buffers. When any
chip on any board is reading, every other DES Cracker chip drives garbage
onto its data pins. The buffer enables were not qualified by the Board Enable
and Chip Enable signals. The initial hardware boards were modified to circumvent
this by providing individual RDB signals to each chip, qualifying them externally
with an FPGA. The correct fix is in top.vhd in the chip VHDL; near the last
line, change:
<PRE> DATA <= DATAO when (RDB = '0' and ADDSEL2 = '0') else (others => 'Z'
</PRE>
<P>
to:
<PRE> DATA <= DATAO when (RDB = '0' and ADDSEL2 = '0' and CHIP_EN = '1')
else (others => 'Z');
</PRE>
<P>
This also involves adding CHIP_EN as an output of upi.vhd.
<P>
</BLOCKQUOTE>
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