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chap-3.html

chap-3.html
Posted Dec 21, 1999

chap-3.html

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chap-3.html

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<!DOCTYPE HTML PUBLIC "html.dtd">
<HTML>
<HEAD>
<TITLE>Cracking DES: Secrets of Encryption Research, Wiretap Politics, and
Chip Design </TITLE>
</HEAD>
<BODY BGCOLOR="#ffffff">

<H1>
<A NAME="3">3</A>
</H1>
<H2>
<I>Design for DES Key Search Array Chip-Level Specification </I>
</H2>
<P>
<P>
<I>In This chapter: </I>
<P>
<UL>
<LI>
<I>ASIC Description </I>
</UL>
<UL>
<LI>
<I>Board description </I>
</UL>
<UL>
<LI>
<I>Read and Write Timing </I>
</UL>
<UL>
<LI>
<I>Addressing Registers </I>
</UL>
<UL>
<LI>
<I>All-active Signal </I>
</UL>
<UL>
<LI>
<I>ASIC Register Allocation</I>
</UL>
<P>
<BR>
Advanced Wireless Technologies, Inc. <BR>
and <BR>
Cryptography Research <BR>
<H3>
<I>ASIC Description </I>
</H3>
<P>
Select1
<BLOCKQUOTE>
Selects Cipher text 1
</BLOCKQUOTE>
<P>
C0
<BLOCKQUOTE>
Cipher text 0
</BLOCKQUOTE>
<P>
C1
<BLOCKQUOTE>
Cipher text 1
</BLOCKQUOTE>
<P>
Search
<BLOCKQUOTE>
Search is active
</BLOCKQUOTE>
<P>
K
<BLOCKQUOTE>
Key
</BLOCKQUOTE>
<P>
Mask
<BLOCKQUOTE>
Plain text bit mask and DES output
</BLOCKQUOTE>
<P>
Match=0
<BLOCKQUOTE>
a Zero is found in any bit position of plain text vector as specified in
step 4 of Search Unit Operation (see Chapter 2)
</BLOCKQUOTE>
<P>
CBC & Extra XOR
<BLOCKQUOTE>
Perform step 3 of Search Unit Operation (see Chapter 2)
</BLOCKQUOTE>
<P>
<I>3-1</I>
<P>
<HR>
<P>
<I>3-2</I>
<P>
<IMG SRC="des3-1.jpg" WIDTH="508" HEIGHT="511">
<P>
<I>Figure 3-1. Search Unit Operation Flow Chart </I><BR>
<P>
To determine the maximum number of bit required for the Key:
<BLOCKQUOTE>
K= log<SUB>2</SUB>(Maximum combinations/number of chips)
<P>
= log<SUB>2</SUB>(2<SUP>56</SUP>/(24 cpc * 64 cpb * 24 boards) =
log<SUB>2</SUB>(1. 95<I>E</I>12) = 42 bits
</BLOCKQUOTE>
<P>
If we are going to use 32-bit counters, then it will overflow every:
<BLOCKQUOTE>
2<SUP>32</SUP> * 16 cycles * 25ns = 1. 72 * 10<SUP>12</SUP>ns = 1720 sec
= 28. 7 minutes
</BLOCKQUOTE>
<P>
<HR>
<P>
<I>3-3</I>
<P>
<IMG SRC="des3-2.jpg" WIDTH="507" HEIGHT="540">
<P>
<I>Figure 3-2 State Diagram tor the Search Unit </I><BR>
<H3>
<I>Board description </I>
</H3>
<P>
The PC will interface with the ASICs through a parallel card. The parallel
card has three ports, assigned:
<BLOCKQUOTE>
Port A: Address(7:0) <BR>
Port B: Data(7:0) <BR>
Port C: Control, 8 signals
</BLOCKQUOTE>
<P>
To reduce the routing resources on the boards and ASICs we multiplex the
address lines. To access register on the ASIC, it is required that the software
latch the
<P>
<HR>
<P>
<I>3-4</I>
<P>
<IMG SRC="des3-3.jpg" WIDTH="506" HEIGHT="600">
<P>
<I>Figure 3-3: Search Unit's Block Diagram </I><BR>
<P>
address three times: Board-ID(7:0), Chip-ID(6:0) and then Register address.
<P>
Having switches on the board makes the design flexible and expandable. Each
board has its own unique Board-ID configured on switches: for example a board
<P>
<HR>
<P>
<I>3-5</I>
<P>
with an ID of hexadecimal 5F has its board ID switches configured as follows:
<P>
<IMG SRC="des3-31.jpg" WIDTH="506" HEIGHT="121">
<P>
<H3>
<I>Read and Write Timing </I>
</H3>
<P>
<IMG SRC="des3-32.jpg" WIDTH="505" HEIGHT="244">
<P>
<HR>
<P>
<I>3-6</I>
<P>
<IMG SRC="des3-33.jpg" WIDTH="510" HEIGHT="246">
<P>
<P>
t<SUB>as1</SUB> 10 ns Min Board-ID and Chip-ID Address setup
<P>
t<SUB>as2</SUB> 10 ns Min Write Register-Address setup
<P>
t<SUB>as3</SUB> 10 ns Min Read Register-Address setup
<P>
t<SUB>ah1</SUB> 10 ns Min Board-ID and Chip-ID Address invalid (hold)
<P>
t<SUB>ah2</SUB> 10 ns Min Write strobe trailing edge to Address invalid (hold)
<P>
t<SUB>av</SUB> 10 ns Min ALE valid
<P>
t<SUB>ds</SUB> 10 ns Min Data valid to Write strobe goes low (setup)
<P>
t<SUB>ch</SUB> 10 ns Min Chip select hold
<P>
t<SUB>dh</SUB> 10 ns Min Write strobe goes high to data invalid (Data hold)
<P>
t<SUB>rv</SUB> 10 ns Min Read strobe duration
<P>
t<SUB>dv</SUB> 100 ns Max Read strobe goes low to data valid
<P>
t<SUB>dh</SUB> 100 ns Max Read strobe goes high to data invalid (Data hold)
<P>
<HR>
<P>
<I>3-7</I>
<H3>
<I>Addressing Registers </I>
</H3>
<P>
<IMG SRC="des3-4.jpg" WIDTH="368" HEIGHT="195">
<P>
<I>Figure 3-4 Address Bus Scheme</I><BR>
<H3>
<I>All-active Signal </I>
</H3>
<P>
If low the SearchActive bit together. We will place one AND gate per ASIC
and cascade them.
<P>
<IMG SRC="des3-41.jpg" WIDTH="508" HEIGHT="118">
<P>
<HR>
<P>
<I>3-8 </I>
<H3>
<I>ASIC Register Allocation </I>
</H3>
<P>
<TABLE BORDER CELLPADDING="12">
<TR>
<TD COLSPAN="2"><P ALIGN="Center">
<B>Registers Common to All Search Units </B></TD>
</TR>
<TR>
<TD>0x00-0x1f</TD>
<TD>PlaintextVector</TD>
</TR>
<TR>
<TD>0x20-0x27</TD>
<TD>PlaintextXorMask</TD>
</TR>
<TR>
<TD>0x28-0x2f</TD>
<TD>CipherText0</TD>
</TR>
<TR>
<TD>0x30-0x37</TD>
<TD>CipherText1</TD>
</TR>
<TR>
<TD>0x38</TD>
<TD>PlaintextByteMask</TD>
</TR>
<TR>
<TD>0x39-0x3e</TD>
<TD>Reserved</TD>
</TR>
<TR>
<TD>0x3f</TD>
<TD>SearchInfo</TD>
</TR>
<TR>
<TD COLSPAN="2"><P ALIGN="Center">
<B>Additional Registers for Search Units </B></TD>
</TR>
<TR>
<TD>0x40-0x47</TD>
<TD>Search Unit 0: Key counter (first 7 bytes) and Search Status</TD>
</TR>
<TR>
<TD>0x48-0x4f</TD>
<TD>Search Unit 1: Key counter (first 7 bytes) and Search Status</TD>
</TR>
<TR>
<TD>. . .</TD>
<TD></TD>
</TR>
<TR>
<TD>0xf8-0xff</TD>
<TD>Search Unit 23: Key counter (first 7 bytes) and Search Status</TD>
</TR>
</TABLE>
<P>
Number of register required:
<P>
58 common registers + 8 * <I>n</I> registers; <I>n</I> = the total number
of search units in an ASIC In this case <I>n</I> = 24, therefore 58 + 192
= 250 registers
<P>
<HR>
<P>
<I>3-9</I>
<P>
<IMG SRC="des3-42.jpg" WIDTH="511" HEIGHT="535">
<P>
Note: The unspecified pins are Non-Connects
<BLOCKQUOTE>
CNTRL0 = ALE = ADDSEL1
<P>
CNTRL1 = CSB = ADDSEL2
</BLOCKQUOTE>
<P>
</BODY></HTML>

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